Such a circuit arrangement comprises a first switching group, enabling or disabling a data line on the basis of voltage, and at least one second switching group, producing two discrete output voltages differing in terms of a voltage swing, whose switching states associated with the discrete output voltages can be stored on a nonvolatile basis, the disabling or enabling of the data line being able to be stipulated by the switching state of the second switching group.
Configurable components have been known for a long time and are referred to generally as programmable logic devices (PLDs), since they preferably perform logic functions. Such PLD components are used primarily for less complex tasks. Logic chips of this kind are known, by way of example, from U.S. Pat. No. 4,870,302 or the publication “Ranmuthu, I. W. et al.; Magneto-resistive elements—An Alternative to Floating Gate Technology; in: Proceedings of the Midwest Symposiums on Circuits and Systems, 1992, pg(s). 134-136 vol. 1”. Such logic chips involve the application program being defined during booting: a program is read from a program store and configurable areas are configured. The configurable areas have the following properties: either they define links between prescribed points (routing areas) or they define the processing of logic input signals to form logic output signals (logic cell areas).
The programming information is distributed in the surface area. The configurability of the PLDs is limited to a few configurable parameters which are set permanently during booting. Two memories are required in this context: an external boot memory chip (discrete chip, e.g. an EEPROM 113 in U.S. Pat. No. 4,870,302) and internal memory cells distributed over the surface area (e.g. as shown in FIGS. 3a and 10a in U.S. Pat. No. 4,870,302 or FIG. 5 in the publication by Ranmutha et al.). After booting, the local memory cells contain information for the links and for the logic functions of the cells.
Fundamental parameters for assessing the performance of these memories are surface area requirement and static (leakage) power consumption as static “costs” and also switching speed and switching capacity as dynamic “costs”. The text which follows considers only nonvolatile, reconfigurable architectures, namely SRAM in combination with Boot-ROM or EEPROM. The SRAM is a relatively large cell, has a fast operating speed and is a volatile memory, whereas the Boot-ROM is slow and nonvolatile. The EEPROM is a medium-sized cell with a slow operating speed, a high configuration power requirement and a low “read” power consumption.
The surface-area efficiency and power-loss efficiency of distributed memory cells is approximately up to two orders of magnitude worse than that of discrete memory chips having the same performance. If the application program requires lower performance than the chips provide, however, the unused areas inevitably likewise produce a power loss. Typical utilization levels for the logic blocks provided in PLDs are approximately 30% to 70%. At one particular time, only fractions of these are actively involved in processing logic information.
The links distributed over the entire chip can be set only by boot operations in the case of conventional components. Dynamic configuration of the links could increase the utilization level.
DE 103 20 701 A1 therefore proposes the use of just a single component integrating a rapidly switchable, nonvolatile memory. Specifically, TMR (Tunnel Magneto-Resistive) cells are proposed for this purpose. Such magneto-resistive elements are distinguished by virtue of their resistive behavior being determined by the condition of the magnetization of a magnetically soft information layer relative to a magnetically hard reference layer. Depending on whether the magnetizations are parallel or in opposition to one another, a low or high resistance is produced across the element. The direction of magnetization of the magnetically soft layer can be changed easily and quickly, to which end a configuration current pulse which is carried by a configuration conductor and produces a magnetic field acting on the magnetization of the magnetically soft layer is used.
The TMR technologies usually available have only a resistance change of 50% between the two discretely switchable resistors, however, that is to say that the ratio of the lower resistance to the higher resistance is approximately 2:3. If one also considers that currently available TMR elements can take a voltage drop of no more than approximately 600 mV without being destroyed, the resistance ratio is in most cases not sufficient to connect a data line to the components described in the prior art, since the resistor elements which can be switched between two states with different discrete resistance values can have only a certain maximum voltage applied to them, and therefore the voltage swing is limited.